// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.


// Generated by Quartus II 64-Bit Version 13.0 (Build Build 232 06/12/2013)
// Created on Sat Jul 19 15:41:36 2014

SP_BUS SP_BUS_inst
(
	.clk(clk_sig) ,	// input  clk_sig
	.rst_n(rst_n_sig) ,	// input  rst_n_sig
	.ADDR(ADDR_sig) ,	// input [11:0] ADDR_sig
	.RD(RD_sig) ,	// input  RD_sig
	.WR(WR_sig) ,	// input  WR_sig
	.DATA(DATA_sig) ,	// inout [15:0] DATA_sig
	.software_rst_n(software_rst_n_sig) ,	// output  software_rst_n_sig
	.cs0(cs0_sig) ,	// output  cs0_sig
	.cs1(cs1_sig) ,	// output  cs1_sig
	.cs2(cs2_sig) ,	// output  cs2_sig
	.cs3(cs3_sig) ,	// output  cs3_sig
	.addr(addr_sig) ,	// output [7:0] addr_sig
	.addr24(addr24_sig) ,	// output [23:0] addr24_sig
	.rddat0(rddat0_sig) ,	// input [15:0] rddat0_sig
	.rddat1(rddat1_sig) ,	// input [15:0] rddat1_sig
	.rddat2(rddat2_sig) ,	// input [15:0] rddat2_sig
	.rddat3(rddat3_sig) ,	// input [15:0] rddat3_sig
	.wrdat(wrdat_sig) 	// output [15:0] wrdat_sig
);

